Testing of integrated circuits (ICs), also called chips, is an important step in determining whether a design and manufacture have been successful in achieving a desired product. Advantageously, initial testing is performed while the chips are still held together as parts of a semiconductor wafer. If testing shows that the performance is defective in some way, then the design, or perhaps the processes employed in fabricating the wafer, can be altered to achieve a desired result.
With the development of higher speed ICs have come special problems resulting from the inherent inductance of the probe wires that are used in testing the ICs. The inductance of a standard probe wire is much too large to permit accurate testing at frequencies above about 100 MHz. Probing apparatus such as that disclosed in U.S. Pat. No. 4,871,964 (Boll et al.), issued on Oct. 3, 1989 and assigned to the same assignee as the present invention, is highly effective for testing ICs up to very high speeds and has been used at frequencies up to 120 GHz. Generally, very high speed prior art techniques tend to be unnecessarily expensive when accuracy is not important or when the ICs or circuits being tested are not high speed.
Still further, applying power to a circuit on a chip during testing can present serious problems. The circuit demands more or less current from the power lead as the internal circuits on the chip switch on and off during testing. The inductance of a probe wire that supplies the electrical current causes the voltage supplied to the chip to vary as the current demanded by the circuit increases and decreases.
A technique for supplying relatively stable power through low impedance transmission lines which use an inflexible capacitor is described in U.S. Pat. No. 4,764,723 (E. Strid), issued on Aug. 16, 1988. More particularly, a wafer probe is disclosed comprising transmission lines having a first impedance, and power supply conductors having a second impedance which is lower than the first impedance, and ground conductors. The transmission lines and the power supply conductors are formed on a first level of a substrate while the ground conductors are formed on a second layer of the substrate. The substrate is tapered so that the transmission lines and power conductors converge to engage minutely spaced bonding pads on a wafer being tested. Fixed bypass networks, such as bypass capacitors, are optionally located where test apparatus is joined to the wafer probe. Accordingly, this structure is relatively complex and more expensive to implement than is desirable in some applications.
It is desirable to provide a probe device for testing high speed integrated circuits and very high speed digital circuits that connects various portions of a circuit on a chip to a testing apparatus for analysis. Still further, it is desirable to provide power during probe testing in a manner that is simple, flexible, and effective.